ADZS-21469-EZLITE【PDF 21/62 页】KIT EVAL EZ LITE ADSP-21469

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Preliminary Technical Data

Use the exact timing information given. Do not attempt to

ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469

acteristics describe what the processor will do in a given

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 41 on Page 52 under Test Conditions for voltage refer-

ence levels.

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

CLK_CFGx/

PMCTL

LINKPORT

CLOCK

DIVIDER

PMCTL

LCLK

PMCTL

CLK_CFGx/

PLL

PMCTL

CLKIN

CLKIN

DIVIDER

PLLI

CLK

LOOP

FILTER

VCO

PLL

DIVIDER

CCLK

DDR2

DIVIDER

DDR2_CLK

XTAL

BUF

PMCTL

PLL

MULTIPLIER

CLK_CFGx/

PMCTL

DIVIDE

BY 2

PCLK

CLK_CFGx/PMCTL

PMCTL

PCLK

CCLK

CLK_CFGx/

PMCTL

MLB S Y S CLK

MLB CLOCK

CLKOUT

PMCTL

DIVIDER

RESET

DELAY OF

4096 CLKIN

RESETOUT

BUF

RESETOUT /

CLKOUT

CYCLE S

CORERST

Figure 3. Core Clock and System Clock Relationship to CLKIN

Rev. PrC

| Page 21 of 62 | January 2009

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